In circuits, especially memories, there are generally some input signals that are used in multiple sections of the circuit. For instance, in a random access memory, RAM, a typical architecture involves arranging the RAM into blocks such that some address bits are decoded to select a block, while other address bits are decoded to select a column within each of the blocks. In prior art circuits, one input buffer is used per address bit. The input buffer is followed by logic which decodes and drives signals across the integrated circuit chip upon which the memory is located. For instance, for the column decode, the buffered address bits may be decoded (or partially decoded) and the decoded (or partially decoded) signals are driven across the integrated circuit chip to each of the blocks. Alternatively, the buffered address bits may be driven across the bar and the decoding can be done at each block.
FIG. 1a illustrates a schematic diagram of a prior art memory architecture as described above. Five inputs, indicated by a slash mark under the numeral 5 (numerous inputs or outputs will hereinafter be shown as a slash mark through a line adjacent a number indicating the number of inputs or outputs), are received by an input buffer from a bond pad area (the input buffer is typically placed near the chip bond pads). The input buffer sends signals to two pre-decoders PD. Pre-decoders PD are connected to line drivers DR (note that a chain of line drivers may be used) which output information to decoders DC. As shown, decoders DC output 32 lines to each memory block for addressing memory in each block. With reference to FIG. 1b, a schematic drawing of a two-to-four pre-decoder is shown. Signals S1 and S2 are each inverted by an associated inverter 4 and combinations of complemented and uncomplemented signals are NANDed by NAND gates 6 shown, to produce four NAND gate outputs. With reference to FIG. 1c, a schematic diagram of pre-decoder PD, and its associated circuitry, connected to decoder DC of FIG. 1a is illustrated. Inputs are received by the three-to-eight decoder and two-to-four decoder shown and transmitted to individual drivers DR. Each output from the three-to-eight decoder is NANDed with each output from the two-to-four decoder by NAND gates 6. The entire interconnect relationship is not shown. Only a sample of the entire interconnect relationship is illustrated wherein the top driver line of the three-to-eight decoder is NANDed with each two-to-four driver line.
FIG. 1d illustrates another prior art memory architecture wherein five lines from an input buffer are sent to individual drivers DR. These drivers transmit information through five lines each to a five-to-thirty-two decoder DC.
Two major problems with prior art circuits and architectures as described above are the delay in generation and the power consumed in driving long capacitive interconnect lines.